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S E M I C O N D U C T O R, I N C .
TQ8101C
The TQ8101C is a SONET/SDH transceiver that integrates Multiplexing, Demultiplexing, SONET/SDH Framing, clock synthesis PLL (MDFP), and loopback functions in a single monolithic integrated circuit. Implementation with the TQ8101C requires only a simple external RC loop filter and standard TTL and ECL power supplies. For optimal performance, the TQ8101C MDFP is packaged in a 68-pin multilayer ceramic (MLC) surface-mount package with an integral CuW heat spreader. The TQ8101C provides an integrated solution for physical interfaces intended for use in STS-12/STM-4 (622.08-Mb/s) and STS-3/STM-1 (155.52-Mb/s) SONET/SDH systems. The TQ8101C meets ANSI, Bellcore, and ITU requirements for a SONET/ SDH device. With a 51.84-MHz reference clock, the phase-locked loop (PLL) provides 77.76-MHz or 19.44-MHz output for the multiplexer and 77.76-MHz or 19.44-MHz and 51.84-MHz output for the demultiplexer. Typical SONET/SDH system applications for the TQ8101C include:
TELECOM PRODUCTS
622/155 Mb/s SONET/SDH MDFP
Features
* Byte-wide Multiplexing, Demultiplexing, Framing, and PLL (MDFP) in one device * Choice of STS-12/STM-4 or STS-3/STM-1 transmission rates * Configurable master or slave reference clock generation and PLL bypass for external clocking * 77.76 MHz or 19.44 MHz output for the multiplexer; 77.76 MHz or 19.44 MHz and 51.84 MHz output for the demultiplexer * External RC loop filter * Pass-through mode and three loopback modes for enhanced filed diagnostics * Frame-synchronous and bytealigned demultiplexer output, compliant with SONET and SDH * Search, detect, and recovery of framing on out-of-frame input * Standard TTL and differential or single-ended ECL I/O (except TXCK) * Tristate TTL output for factory circuit-board testability * 68-pin TriQuint MLC controlled-Z surface-mount package with integral heat spreader
* * * * * *
Transmission system transport cards Switch and cross-connect line cards Repeaters ATM physical layer interfaces Test equipment Add/drop multiplexers
Figure 1. Logical Application
TQ8101C MDFP
MXDT(7:0) DXDT(7:0) OOF MXCK0 DXSYNC DXCK O/E Rx + TQ8103 CDR OC-3 or OC-12 Driver and LASER OC-3 or OC-12 600 0.68 F VEE
PM5312 or PM5355 STTX S/UNI-622 TOUT(7:0) RIN(7:0) OHFP OOF TCLK RIFP RICLK CNTL(3:0) 8-bit data 8-bit data OOF fix*
51.84 MHz CMOS OSC
*Contact PMC-Sierra for application note.
* Dual-supply operation (+5V, -5.2V) * Low power dissipation (2.3W nom.)
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TQ8101C
Figure 2. TQ8101C Block Diagram
MXDT(7:0)
Mux
2
TXDT TXCK
CNTL(3:0) MO
Control Block
Serial-to-Parallel Converter
Loopback Block
2 2
RXDT RXCK
TUNE IOUT MXCK(2:0)
PLL Clock Synthesizer
Mux
+5V GND -5.2V
MXHC MXLRC DXRCK DXCK DXDT(7:0)
2
Framer
DXSYNC
Demux
OOF
Figure 3. TQ8101C Package--68-pin MLC
1.170 .006 .950 .010 .800
4 plcs Pin 1 index
1 2 3 4
A
A .950
.010
Ceramic or metal lid
.050
n-4 plcs
.016
n plcs
CuW heat spreader
Chip capacitor
4 plcs
TOP VIEW
BOTTOM VIEW
.060 .005
.650 .005
.125
.050
SECTION A
A
2
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TQ8101C
Functional Description
Figure 2 shows a block diagram of the TQ8101C multiplexer, demultiplexer, framer, and PLL clock synthesizer (MDFP). The primary purpose of TQ8101C is to integrate the conversion of serial and parallel SONET/SDH data with bit alignment and clock synthesis in a single device. Multiplexing Byte-wide input data on MXDT(7:0)1 is continuously strobed into the multiplexer on the rising edge of the multiplexer clock output, MXCK(2:0).2 Any of these three MXCK pins may be used as a reference point for relative timing. (See Table 8 for setup, hold, and skew times. See Table 1 for clock selection options.) Either an on-chip synthesized clock (see "PLL Clock Synthesis") or an external high-speed multiplexer
clock, MXHC, serializes the input data bytes. In the normal mode of operation, the serial data is then buffered as ECL-compatible output on TXDT. An ECL output is provided for the transmit clock, TXCK.
PRODUCTS
Demultiplexing As shown in Figure 4, The demultiplexer block converts incoming serial data on DXDTIN3. Byte-wide output data is presented on DXDT(7:0)4 slightly after the falling edge of the output demultiplexer clock, DXCK. (See Table 8 for setup, hold, and skew times.) The demultiplexer block also includes clock divider circuitry, which is used by the demultiplexer to control divide-by-8 output on DXCK. The MDFP provides a divide-by-3 or divide-by-12 output, DXRCK. (See Table 1 for mode selection options.)
Figure 4. Demultiplexer Functional Block
DXDTIN DXHSCK Shift Register Parallel Register DXDT(7:0)
XFD OOF
Frame Detection and Recovery
DXSYNC
1/8 1/2 1/3 RT 1/3 1/2 Mux
DXCK
DXRCK
Notes:
1. MXDT(0) is defined as the least significant bit. 2. MXCK(2:0) nominally runs at 77.76 MHz in STS-12/STM-4 mode, and at 19.44 MHz in STS-3/STM-1 mode. 3. Internal signal. See Figure 5, "TQ8101C Loopback Modes." 4. DXDT (0) is defined as the least significant bit.
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SONET/SDH/ATM TELECOM
TQ8101C
Framing The demultiplexer block (see Figure 2) includes a frame-detection and recovery block. Regardless of the state of the OOF input signal, this block takes DXSYNC high for one period of DXCK whenever it detects a pattern of three "A1" bytes followed by three "A2" bytes. Frame recovery is initiated by the rising edge of the OOF input signal. The recovery process involves a search for a bit rotation that satisfies the three-"A1"- three-"A2" byte pattern specified for SONET/SDH. Once the pattern is found, DXSYNC goes high and the bit rotation is synchronized to the correct byte boundaries. No further byte boundary adjustments are made, regardless of "A1"-"A2" indication, unless they have been preceded by an OOF rising edge.
PLL Clock Synthesis The PLL utilizes a monolithic voltage-controlled oscillator with a typical tuning constant of 50 to 100 MHz per volt on the TUNE input. This configuration provides jitter performance superior to other technologies. In a typical SONET/SDH application the TUNE input and charge pump output IOUT are connected and tied to VEE through a 600-ohm resistor and 0.68-F capacitor. Loopback The TQ8101C features four loopback modes: normal (pass-through), equipment loopback, split loopback, and facility loopback. Loopback modes are controlled by pins CNTL(3:0). Note that the loopback mode does not affect the latched selection of clock modes and rates. Note that the RXCK input is directly connected to the TXCK output in most loopback modes (see below).
Figure 5. TQ8101C Loopback Modes
Normal RXDT RXCK TXDT TXCK DXDTIN DXHSCK MXDTOUT MXHSCK TXDT TXCK Equipment Loopback DXDTIN DXHSCK MXDTOUT MXHSCK
Split Loopback RXDT RXCK TXDT TXCK DXDTIN DXHSCK MXDTOUT MXHSCK
Facility Loopback RXDT RXCK TXDT TXCK DXDTIN DXHSCK
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TQ8101C
Control The signals on pins CNTL(3:0) can be used to control the clock rate, clock mode, loopback scheme, and tristate pins. Also, the internal PLL high-speed clock may be disabled, allowing an external clock source to be used on the MXHCN and MXHCP pins. Note that the NAND tree enable normally is used only for device testing of the VIH and VIL parameters. At power-up or during initialization, CNTL(3) should be set to logic 1. During reset, all internal counters, dividers, and loopback states, and the phasefrequency detector, are reset or deactivated. Note that frame search is initiated only by a rising edge on OOF.
SONET/SDH/ATM TELECOM
Table 1. Modes of Operation
CNTL(3:0)
0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh
Notes: * * * *
Modes of operation
Reset Tristate all TTL outputs except DXRCK and MO NAND-tree test all TTL inputs except CNTL(3:0) DXRCK tristate Frame recovery disable Equipment loopback Facility loopback Split loopback Bypass, slave, internal VCO disabled, STS-3 rate Bypass, master, internal VCO disabled, STS-3 rate Bypass, slave, internal VCO disabled, STS-12 rate Bypass, master, internal VCO disabled, STS-12 rate Normal, slave, internal VCO enabled, STS-3 rate Normal, master, internal VCO enabled, STS-3 rate Normal, slave, internal VCO enabled, STS-12 rate Normal, master, internal VCO enabled, STS-12 rate
"Bypass" indicates the use of the external high-speed clock in lieu of the internal transmit PLL. "Normal" indicates use of the internal transmit PLL. "Master" derives PLL timing from the reference 51.84-MHz oscillator input, MXLRC "Slave" derives PLL timing from the demultiplexer clock input, RXCK.
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PRODUCTS
TQ8101C
Table 2. Absolute Maximum Ratings
Parameter
Positive supply Negative supply Output voltage Output current Input voltage Input current Output voltage Output current Input voltage Input current Junction temperature Storage temperature
Symbol
VCC VEE VO IO VI II VO IO VI II TJ TS
Level
-- -- ECL ECL ECL ECL TTL TTL TTL TTL -- --
Minimum
0 -7 VEE - 0.5 -- VEE - 0.5 -1 -0.5 -- -0.5 -1 -55 -65
Maximum
7 0 +0.5 40 +0.5 1 VCC + 0.5 20 VCC + 0.5 1 +150 +175
Unit
V V V mA V mA V mA V mA C C
Table 3. Recommended Operating Conditions
Parameter
Positive supply Negative supply Operating ambient temperature
Symbol
VCC VEE TO
Minimum
4.75 -5.5 0
Nominal
5 -5.2
Maximum
5.25 -4.75 70
Unit
V V C
Table 4. Power Consumption
Function
Nominal Max
+5 V supply
40 55
-5.2 V supply
320 420
Unit
mA mA
Parameter
Thermal resistance, junction-case
Symbol
JC
Level
Minimum
Maximum
4
Unit
C / W
6
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TQ8101C
Figure 6. Pinout Diagram (heat spreader side--top view)
33 DXSYN 30 DXDT0 29 DXDT1 27 DXDT2 26 DXDT3 24 DXDT4 23 DXDT5 21 DXDT6 20 DXDT7 32 DXCK 34 GND 31 GND 28 GND 25 GND 22 GND 19 GND 18 VCC
SONET/SDH/ATM TELECOM
35 VEE 36 GND 37 MXDT7 38 MXDT6 39 GND 40 MXDT5 41 MXDT4 42 GND 43 MXDT3 44 MXDT2 45 GND 46 MXDT1 47 MXDT0 48 GND 49 MXCK2 50 MXCK1 51 GND
17 GND 16 DXRC 15 OOF 14 GND 13 MO 12 TXDTN 11 GND
TQ8101C MDFP
10 TXDTP 9 TXCK 8 GND 7 RXDTP 6 RXDTN 5 GND 4 RXCKN 3 RXCKP 2 GND 1 VEE
57 MXHCN
58 MXHCP
55 MXLRC
54 MXCK0
60 CNTL3
64 CNTL2
66 CNTL1
67 CNTL0
63 TUNE
61 IOUT
53 GND
56 GND
59 GND
62 GND
65 GND
Figure 7. Recommended Package Footprint
.026 .096
1.150
1.150
68 GND
52 VCC
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PRODUCTS
TQ8101C
Table 5. Signal Descriptions
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Signal
VEE GND RXCKP RXCKN GND RXDTN RXDTP GND TXCK TXDTP GND TXDTN MO GND OOF DXRCK GND VCC GND DXDT7 DXDT6 GND DXDT5 DXDT4 GND DXDT3 DXDT2 GND DXDT1 DXDT0 GND DXCK DXSYNC GND
Type
Description
Negative power supply input (-5.2V) Ground Receive bit-serial clock; differential ECL, positive Receive bit-serial clock; differential ECL, negative Ground Receive bit-serial data (MSB first); differential ECL, negative Receive bit-serial data (MSB first); differential ECL, positive Ground Transmit bit-serial clock; single-ended ECL level Transmit bit-serial data (MSB first); differential ECL, positive Ground Transmit bit-serial data (MSB first); differential ECL, negative NAND tree monitor output; TTL level Ground Out of frame; TTL level; rising-edge initiated frame search Demultiplexer reference clock; TTL level; 50-pF backplane driving capacity Ground Positive power supply input (+5.0V) Ground Demultiplexer byte-serial data (bit 7); TTL level Demultiplexer byte-serial data (bit 6); TTL level Ground Demultiplexer byte-serial data (bit 5); TTL level Demultiplexer byte-serial data (bit 4); TTL level Ground Demultiplexer byte-serial data (bit 3); TTL level Demultiplexer byte-serial data (bit 2); TTL level Ground Demultiplexer byte-serial data (bit 1); TTL level Demultiplexer byte-serial date (bit 0); TTL level Ground Demultiplexer byte-serial clock; TTL level Demultiplexer synchronization; TTL level Ground
In In In In Out Out Out Out In Tri Out
Tri Out Tri Out Tri Out Tri Out Tri Out Tri Out Tri Out Tri Out Tri Out Tri Out
(Continues on next page)
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TQ8101C
Table 5. Signal Descriptions (continued)
Pin
35
36 37 38 39 40 41 42
Signal
VEE
GND MXDT7 MXDT6 GND MXDT5 MXDT4 GND
Type
Description
Negative power supply input (-5.2V) PRODUCTS
Ground
In In In In
Multiplexer byte-serial data (bit 7); TTL level Multiplexer byte-serial data (bit 6); TTL level Ground Multiplexer byte-serial data (bit 5); TTL level Multiplexer byte-serial data (bit 4); TTL level Ground
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
MXDT3 MXDT2 GND MXDT1 MXDT0 GND MXCK2 MXCK1 GND VCC GND MXCK0 MXLRC GND MXHCN MXHCP GND CNTL3 IOUT GND TUNE CNTL2 GND CNTL1 CNTL0 GND
In In In In Tri Out Tri Out
Multiplexer byte-serial data (bit 3); TTL level Multiplexer byte-serial data (bit 2); TTL level Ground Multiplexer byte-serial data (bit 1); TTL level Multiplexer byte-serial data (bit 0); TTL level Ground Multiplexer byte-serial clock (bit 2); TTL level. See Table 1 for output rate. Multiplexer byte-serial clock (bit 1); TTL level. See Table 1 for output rate. Ground Positive power supply input (+5.0V) Ground Multiplexer byte-serial clock (bit 0); TTL level. See Table 1 for output rate. Multiplexer low-speed reference clock (51.84 MHz); TTL level Ground Multiplexer high-speed reference clock (max. 640 MHz); differential ECL, negative Multiplexer high-speed reference clock (max. 640 MHz); differential ECL, positive Ground Control (bit 3); TTL level Tristate charge pump output (analog); connect to pin 63 Ground VCO tune (analog); connect to external loop filter and pin 61 Control (bit 2); TTL level Ground Control (bit 1); TTL level Control (bit 0); TTL level Ground
Tri Out In In In In Out In In In In
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SONET/SDH/ATM TELECOM
TQ8101C
Table 6. DC Characteristics--ECL I/O (1)
Parameter
Internal ECL reference Common mode voltage Differential voltage Input HIGH voltage Input LOW voltage Output HIGH voltage Output LOW voltage Input HIGH current Input LOW current Output HIGH current Output LOW current Input capacitance Output capacitance ESD breakdown
Condition
(2) (3) (3) (4) (5) (5) VIH (MAX) VIL (MIN) (6) (6)
Symbol
VREF VCOM VDIFF VIH VIL VOH VOL IIH IIL IOH IOL CIN COUT VESD
Minimum
-- -1500 200 -1100 VEE -1000 VTT - 100 -- -- 20 -2 -- -- 500
Nominal
0.26 VEE -- -- -- -- 0 -- -- -- 23 5 3 3 --
Maximum
-1100 1200 -400 -1500 -500 -1600 30 -30 30 8 -- -- --
Unit
mV mV mV mV mV mV mV mA mA mA mA pF pF V
(1)
Table 7. DC Characteristics--TTL I/O (1)
Parameter
Input HIGH voltage Input LOW voltage Input HIGH current Input LOW current Output HIGH voltage Output LOW voltage Tristate current Input capacitance Output capacitance ESD breakdown
Condition
Symbol
VIH VIL IIH IIL VOH VOL IOZ CIN COUT VESD
Minimum
2.0 0 -- -100 2.4 0 -100 -- -- 1000
Nominal
-- -- -- -- -- -- -- 8 10 --
Maximum
VCC 0.8 100 -- VCC 0.4 100 -- -- --
Unit
V V mA mA V V mA pF pF V
VIH (MAX) VIL (MIN) IOH = 3 mA IOL = -1 mA
(1)
Notes (tables 6 and 7): 1. Specifications apply over recommended operating ranges. 2. Single-ended inputs 3. Differential inputs 4. VREF = -1300 mV 5. RLOAD = 50 ohms to VTT = -2.0V 6. Not tested; consistent with VOH and VOL tests
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TQ8101C
Table 8. AC Characteristics
Parameter
RXCK clock period MXHC clock period TXCK clock period MXCK clock period DXCK clock period MXLRC clock period DXRCK clock period RXCK clock duty cycle MXHC clock duty cycle TXCK clock duty cycle MXCK clock duty cycle DXCK clock duty cycle MXLRC clock duty cycle DXRCK clock duty cycle High-speed rise/fall time1 (more than 79 MHz) Low-speed rise/fall time1 (less than 79 MHz) CNTL(2:0) Setup Time to CNTL(3) CNTL(2:0) Hold Time to CNTL(3) RXDT setup time to RXCK RXDT hold time to RXCK OOF rising edge before A1 changes to A2 OOF pulse width DXSYNC rising edge from parallel data output change from A1 to A2 DXSYNC pulse width DXCK falling edge to valid parallel data output MXDT(0:7) setup time to MXCK MXDT(0:7) hold time to MXCK TXCK falling edge to TXDT
Notes: 1. 20% to 80% of min VOH and max VOL levels.
Symbol
TC(RXCK) TC(MXHC) TC(TXCK) TC(MXCK) TC(DXCK) TC(MXTRC) TC(DXRCK) TDC(RXCK) TDC(MXHC) TDC(TXCK) TDC(MXCK) TDC(DXCK) TDC(MXIRC) TDC(DXRCK) TH(R/F) TL(R/F) TS(CNTL) TH(CNTL) TS(RXDT) TH(RXDT) T(OOFH) T(OOFPW) T(DSYNC) T(DXSYNCPW) TP(DXDT) TS(MXDT) TH(MXDT) TP(TXDT)
Minimum
1.6 1.6 1.6 12.8 12.8 18.87 4.80 30 30 40 40 40 30 40 -- -- 5500 2000 225 125 51.44 12.86 -- 12.86 TC(RXCK) 4500 -2000 --
Nominal
-- -- -- -- -- 19.29 19.29 50 50 50 50 50 50 50 -- -- -- -- -- -- -- -- 25.72 -- TC(RXCK) + 0.5 -- -- --
Maximum
-- -- -- -- -- 19.61 -- 70 70 60 60 60 70 60 320 2.56 -- -- -- -- -- -- -- -- TC(RSCK) + 1.5 -- -- 500
Unit
ns
SONET/SDH/ATM TELECOM
ns ns ns ns % % % % % % % ps ns ps ps ps ps ns ns ns ns ns ps ps ps
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11
PRODUCTS
ns ns
TQ8101C
Figure 8. Input Timing
RXCKP
TS(RXDT) RXDT
TH(RXDT)
MXCK(2:0)
TS(MXDT) MXDT(7:0)
TH(MXDT)
Figure 9. Output Timing
TXCK
TP(TXDT) TXDT
DXCK
TP(DXDT) DXDT(7:0)
TP(DXSYNC) DXSYNC
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TQ8101C
Figure 10. Multiplexer Timing
MXCK(2:0)
SONET/SDH/ATM TELECOM
MXDT(7:0)
TXCK
TXDT
Figure 11. Demultiplexer Timing
RXCK
RXDT
A1 #1
A1 #2
A1 #n
A2 #1
A2 #2
A2 #3
OOF T(OOFH) T(DXSYNC)
T(OOFPW)
DXSYNC T(DXSYNCPW) DXCK DXCK Resync DXDT(7:0) A1 #1 A1 #2 A1 #n A2 #1 A2 #2 A2 #3
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13
PRODUCTS
TQ8101C
SONET/SDH Considerations
Jitter Tolerance This measurement does not apply to the TQ8101C, since data is transmitted from the input parallel bus relative to a TQ8101C-generated clock output (MXCK[2:0]). The user must meet setup and hold time requirements in order to ensure that data tracking is maintained. Jitter Generation By exploiting material characteristics, fully differential SCFL logic, and on-chip reactive elements, the TQ8101C typically has a jitter generation of 0.008 UI RMS (where 1 UI is 1/622.08E06) using recommended loop filter component values.
Ordering Information
TQ8101-M
SONET/SDH MDFP
Evaluation Board Please contact a TriQuint representative or the factory
for availability and pricing.
Additional Information
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: sales@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900
For technical questions and additional information on specific applications: Email: applications@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright (c) 1997 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.1.A November 1997
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